ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 307

• Manufacturer Part Number: ATMEGA128-16MN
• Description: MCU AVR 128KB FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PROG_COMMANDS
($5)
PROG_PAGELOAD
($6)
PROG_PAGEREAD
($7)
Data Registers
2467V–AVR–02/11
The AVR specific public JTAG instruction for entering programming commands via the JTAG
port. The 15-bit Programming Command Register is selected as data register. The active states
are the following:
•
•
•
•
The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port.
The 2048-bit Virtual Flash Page Load Register is selected as data register. This is a virtual scan
chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8-
bit. Unlike most JTAG instructions, the Update-DR state is not used to transfer data from the
Shift Register. The data are automatically transferred to the Flash page buffer byte by byte in the
Shift-DR state by an internal state machine. This is the only active state:
•
Note:
The AVR specific public JTAG instruction to read one full Flash data page via the JTAG port.
The 2056-bit Virtual Flash Page Read Register is selected as data register. This is a virtual scan
chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift Regis-
ter is 8-bit. Unlike most JTAG instructions, the Capture-DR state is not used to transfer data to
the Shift Register. The data are automatically transferred from the Flash page buffer byte by
byte in the Shift-DR state by an internal state machine. This is the only active state:
•
Note:
The data registers are selected by the JTAG instruction registers described in section
ming Specific JTAG Instructions” on page
operations are:
•
•
•
•
•
Capture-DR: the result of the previous command is loaded into the data register.
Shift-DR: the data register is shifted by the TCK input, shifting out the result of the previous
command and shifting in the new command.
Update-DR: the programming command is applied to the Flash inputs.
Run-Test/Idle: one clock cycle is generated, executing the applied command.
Shift-DR: Flash page data are shifted in from TDI by the TCK input, and automatically
loaded into the Flash page one byte at a time.
Shift-DR: Flash data are automatically read one byte at a time and shifted out on TDO by the
TCK input. The TDI input is ignored.
Reset Register
Programming Enable Register
Programming Command Register
Virtual Flash Page Load Register
Virtual Flash Page Read Register
The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first device in
JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise program-
ming algorithm must be used.
The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the first device in
JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise program-
ming algorithm must be used.
305. The data registers relevant for programming
ATmega128
“Program-
307