ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 101

• Manufacturer Part Number: ATMEGA128-16MN
• Description: MCU AVR 128KB FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer/Counter
Timing Diagrams
2467V–AVR–02/11
PWM frequency for the output when using phase correct PWM can be calculated by the follow-
ing equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR0 Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the out-
put will be continuously low and if set equal to MAX the output will be continuously high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of Period 2 in
is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM.
There are two cases that give a transition without Compare Match:
•
•
Figure 41
is a synchronous design and the timer clock (clk
The figure shows the count sequence close to the MAX value.
same timing data, but with the prescaler enabled. The figures illustrate when interrupt flags are
set.
The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clk
is therefore shown as a clock enable signal. In asynchronous mode, clk
the Timer/Counter Oscillator clock. The figures include information on when interrupt flags are
set.
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 41. Timer/Counter Timing Diagram, No Prescaling
Figure 42
OCR0 changes its value from MAX, like in
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
The timer starts counting from a higher value than the one in OCR0, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
Figure 41
TCNTn
(clk
TOVn
clk
clk
I/O
I/O
Tn
and
/1)
shows the same timing data, but with the prescaler enabled.
Figure 42
contains timing data for basic Timer/Counter operation. The figure shows the
MAX - 1
contain timing data for the Timer/Counter operation. The Timer/Counter
Figure 40
f
OCnPCPWM
OCn has a transition from high to low even though there
MAX
Figure
T0
=
) is therefore shown as a clock enable signal.
----------------- -
N 510
f
clk_I/O
⋅
40. When the OCR0 value is MAX the
BOTTOM
Figure 43
I/O
and
ATmega128
should be replaced by
Figure 44
BOTTOM + 1
show the
101
T0
)