ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 31

• Manufacturer Part Number: ATMEGA128-16MN
• Description: MCU AVR 128KB FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2467V–AVR–02/11
• Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit
It is possible to configure different wait-states for different External Memory addresses. The
external memory address space can be divided in two sectors that have separate wait-state bits.
The SRL2, SRL1, and SRL0 bits select the split of the sectors, see
default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address
space is treated as one sector. When the entire SRAM address space is configured as one sec-
tor, the wait-states are configured by the SRW11 and SRW10 bits.
Table 3. Sector limits with different settings of SRL2..0
• Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait-state Select Bits for Upper Sector
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-
nal memory address space, see
• Bit 3..2 – SRW01, SRW00: Wait-state Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-
nal memory address space, see
Table 4. Wait States
Note:
• Bit 0 – Res: Reserved Bit
This is a reserved bit and will always read as zero. When writing to this address location, write
this bit to zero for compatibility with future devices.
SRWn1
SRL2
0
0
1
1
0
0
0
0
1
1
1
1
1. n = 0 or 1 (lower/upper sector).
SRWn0
For further details of the timing and wait-states of the External Memory Interface, see Figures
13 through Figures 16 for how the setting of the SRW bits affects the timing.
0
1
0
1
SRL1
0
0
1
1
0
0
1
1
(1)
Wait States
No wait-states
Wait one cycle during read/write strobe
Wait two cycles during read/write strobe
Wait two cycles during read/write and wait one cycle before driving out
new address
SRL0
0
1
0
1
0
1
0
1
Table
Table
Sector Limits
Lower sector = N/A
Upper sector = 0x1100 - 0xFFFF
Lower sector = 0x1100 - 0x1FFF
Upper sector = 0x2000 - 0xFFFF
Lower sector = 0x1100 - 0x3FFF
Upper sector = 0x4000 - 0xFFFF
Lower sector = 0x1100 - 0x5FFF
Upper sector = 0x6000 - 0xFFFF
Lower sector = 0x1100 - 0x7FFF
Upper sector = 0x8000 - 0xFFFF
Lower sector = 0x1100 - 0x9FFF
Upper sector = 0xA000 - 0xFFFF
Lower sector = 0x1100 - 0xBFFF
Upper sector = 0xC000 - 0xFFFF
Lower sector = 0x1100 - 0xDFFF
Upper sector = 0xE000 - 0xFFFF
4.
4.
Table 3
ATmega128
and
Figure
11. By
31