ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 186
![MCU AVR 128KB FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128-16MN
Manufacturer Part Number
ATMEGA128-16MN
Description
MCU AVR 128KB FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Multi-processor
Communication
Mode
186
ATmega128
Table 75. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X =
0)
Table 76. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X =
1)
The recommendations of the maximum receiver baud rate error was made under the assump-
tion that the receiver and transmitter equally divides the maximum total error.
There are two possible sources for the receivers baud rate error. The receiver’s system clock
(XTAL) will always have some minor instability over the supply voltage range and the tempera-
ture range. When using a crystal to generate the system clock, this is rarely a problem, but for a
resonator the system clock may differ more than 2% depending of the resonators tolerance. The
second source for the error is more controllable. The baud rate generator can not always do an
exact division of the system frequency to get the baud rate wanted. In this case an UBRR value
that gives an acceptable low error can be used if possible.
Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering
function of incoming frames received by the USART receiver. Frames that do not contain
address information will be ignored and not put into the receive buffer. This effectively reduces
the number of incoming frames that has to be handled by the CPU, in a system with multiple
MCUs that communicate via the same serial bus. The transmitter is unaffected by the MPCM
setting, but has to be used differently when it is a part of a system utilizing the Multi-processor
Communication mode.
If the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi-
cates if the frame contains data or address information. If the receiver is set up for frames with 9
data bits, then the ninth bit (RXB8) is used for identifying address and data frames. When the
frame type bit (the first stop or the 9th bit) is one, the frame contains an address. When the
frame type bit is zero the frame is a data frame.
# (Data+Parity Bit)
# (Data+Parity Bit)
10
10
D
D
5
6
7
8
9
5
6
7
8
9
R
R
93.20
94.12
94.81
95.36
95.81
96.17
94.12
94.92
95.52
96.00
96.39
96.70
slow
slow
%
%
R
106.67
105.79
105.11
104.58
104.14
103.78
R
105.66
104.92
104.35
103.90
103.53
103.23
fast
fast
%
%
+5.79/-5.88
+5.11/-5.19
+4.58/-4.54
+4.14/-4.19
+3.78/-3.83
+5.66/-5.88
+4.92/-5.08
+4.35/-4.48
+3.90/-4.00
+3.53/-3.61
+3.23/-3.30
Max Total
+6.67/-6.8
Max Total
Error %
Error %
Recommended Max
Recommended Max
Receiver Error %
Receiver Error %
±3.0
±2.5
±2.0
±2.0
±1.5
±1.5
±2.5
±2.0
±1.5
±1.5
±1.5
±1.0
2467V–AVR–02/11
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