ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 104
![MCU AVR 128KB FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128-16MN
Manufacturer Part Number
ATMEGA128-16MN
Description
MCU AVR 128KB FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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104
ATmega128
Table 52. Waveform Generation Mode Bit Description
Note:
• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits
are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set
in order to enable the output driver.
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0
bit setting.
normal or CTC mode (non-PWM).
Table 53. Compare Output Mode, non-PWM Mode
Table 54
mode.
Table 54. Compare Output Mode, Fast PWM Mode
Note:
Table 55
PWM mode.
Mode
COM01
0
1
2
3
COM01
0
0
1
1
0
0
1
1
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare
WGM01
shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase correct
shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast PWM
(CTC0)
Table 53
However, the functionality and location of these bits are compatible with previous versions of
the timer.
match is ignored, but the set or clear is done at BOTTOM. See
for more details.
0
0
1
1
COM00
(1)
COM00
0
1
0
1
0
1
0
1
shows the COM01:0 bit functionality when the WGM01:0 bits are set to a
WGM00
(PWM0)
0
1
0
1
Description
Normal port operation, OC0 disconnected.
Reserved
Clear OC0 on compare match, set OC0 at BOTTOM,
(non-inverting mode)
Set OC0 on compare match, clear OC0 at BOTTOM,
(inverting mode)
(1)
Description
Normal port operation, OC0 disconnected.
Toggle OC0 on compare match
Clear OC0 on compare match
Set OC0 on compare match
Timer/Counter
Mode of Operation
Normal
PWM, Phase
Correct
CTC
Fast PWM
(1)
TOP
0xFF
0xFF
OCR0
0xFF
Update of
OCR0 at
Immediate
TOP
Immediate
BOTTOM
“Fast PWM Mode” on page 98
TOV0 Flag
Set on
MAX
BOTTOM
MAX
MAX
2467V–AVR–02/11
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