ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 185
![MCU AVR 128KB FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128-16MN
Manufacturer Part Number
ATMEGA128-16MN
Description
MCU AVR 128KB FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Asynchronous
Operational Range
2467V–AVR–02/11
Figure 85. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FE) flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in
(C) marks a stop bit of full length. The early start bit detection influences the operational range of
the receiver.
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see
Table
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
D
S
S
S
R
baud rate. R
the receiver baud rate.
Table 75
normal speed mode has higher toleration of baud rate variations.
F
M
slow
(U2X = 0)
(U2X = 1)
Sample
Sample
is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver
Sum of character size and parity size (D = 5 to 10-bit)
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
mode.
First sample number used for majority voting. S
for Double Speed mode.
Middle sample number used for majority voting. S
S
RxD
75) base frequency, the Receiver will not be able to synchronize the frames to the start bit.
M
and
= 5 for Double Speed mode.
R
slow
fast
Table 76
is the ratio of the fastest incoming data rate that can be accepted in relation to
=
Figure
------------------------------------------ -
S 1
–
1
1
list the maximum receiver baud rate error that can be tolerated. Note that
(
D
+
2
85. For Double Speed mode the first low level must be delayed to (B).
+
D S ⋅
1
3
2
)S
+
4
S
F
5
3
6
7
4
8
STOP 1
9
5
F
10
= 8 for Normal Speed and S
M
R
= 9 for Normal Speed and
fast
(A)
0/1
6
=
0/1
-----------------------------------
(
D
(B)
0/1
0/1
(
+
D
1
+
)S
2
ATmega128
)S
+
S
M
(C)
F
= 4
185
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