ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 137
ATMEGA128-16MN
Manufacturer Part Number
ATMEGA128-16MN
Description
MCU AVR 128KB FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Timer/Counter1 –
TCNT1H and TCNT1L
Timer/Counter3 –
TCNT3H and TCNT3L
Output Compare
Register 1 A –
OCR1AH and OCR1AL
Output Compare
Register 1 B –
OCR1BH and OCR1BL
Output Compare
Register 1 C –
OCR1CH and OCR1CL
Output Compare
Register 3 A –
OCR3AH and OCR3AL
2467V–AVR–02/11
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This Temporary Register is shared by all the other 16-bit registers.
bit Registers” on page 114.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-
pare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock
for all compare units.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
R/W
R/W
OCR1A[15:8]
OCR1B[15:8]
OCR1C[15:8]
OCR3A[15:8]
4
TCNT1[15:8]
0
4
TCNT3[15:8]
0
4
0
4
0
4
0
4
0
OCR1A[7:0]
OCR1B[7:0]
OCR1C[7:0]
OCR3A[7:0]
TCNT1[7:0]
TCNT3[7:0]
R/W
R/W
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
1
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
ATmega128
0
0
0
0
0
0
0
0
0
0
0
0
See “Accessing 16-
OCR1AH
OCR1BH
OCR1CH
OCR3AH
OCR1AL
OCR1BL
OCR1CL
OCR3AL
TCNT1H
TCNT1L
TCNT3H
TCNT3L
137
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