ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 89

• Manufacturer Part Number: ATMEGA128-16MN
• Description: MCU AVR 128KB FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External
Interrupts
External Interrupt
Control Register A –
EICRA
2467V–AVR–02/11
The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts
will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of gen-
erating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or
a low level. This is set up as indicated in the specification for the External Interrupt Control Reg-
isters – EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is
configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that
recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock,
described in
edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be
used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in
all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. This makes the MCU less sensitive to
noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the
Watchdog Oscillator is 1µs (nominal) at 5.0V and 25°C. The frequency of the Watchdog Oscilla-
tor is voltage dependent as shown in the
wake up if the input has the required level during this sampling or if it is held until the end of the
start-up time. The start-up time is defined by the SUT fuses as described in
their Distribution” on page
disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be
generated. The required level must be held long enough for the MCU to complete the wake up to
trigger the level interrupt.
This Register can not be reached in Atmel
value defines INT3:0 as low level interrupts, as in ATmega103.
• Bits 7..0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in
nously. Pulses on INT3:0 pins wider than the minimum pulse width given in
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an inter-
rupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur.
Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the
EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be
cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the
interrupt is re-enabled.
Bit
Read/Write
Initial Value
“Clock Systems and their Distribution” on page
ISC31
R/W
7
0
ISC30
R/W
6
0
35. If the level is sampled twice by the Watchdog Oscillator clock but
ISC21
R/W
5
0
Table
ISC20
R/W
4
0
“Electrical Characteristics” on page
®
AVR
48. Edges on INT3..INT0 are registered asynchro-
ISC11
R/W
3
0
®
ATmega103 compatibility mode, but the initial
ISC10
R/W
2
0
35. Low level interrupts and the
ISC01
R/W
1
0
ISC00
R/W
ATmega128
0
0
“Clock Systems and
318. The MCU will
EICRA
Table 49
will
89