ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 265

MCU AVR 128KB FLASH 16MHZ 64QFN

ATMEGA128-16MN

Manufacturer Part Number
ATMEGA128-16MN
Description
MCU AVR 128KB FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128-16MN

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
2467V–AVR–02/11
Table 105. Algorithm for Using the ADC
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
Step
9
10
11
Actions
Verify the
COMP bit
scanned
out to be 1
ADCEN
1
1
1
DAC
0x143
0x143
0x200
MUXEN
0x08
0x08
0x08
HOLD
1
1
1
PRECH
1
0
1
PA3.
Data
0
0
0
PA3.
Control
0
0
0
ATmega128
hold,max
PA3.
Pullup_
Enable
0
0
0
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