ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 259

• Manufacturer Part Number: ATMEGA128-16MN
• Description: MCU AVR 128KB FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Scanning the Analog
Comparator
2467V–AVR–02/11
Figure 128. Boundary-scan Cells for Oscillators and Clock Options
Table 102
XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.
Table 102. Scan Signals for the Oscillators
Notes:
The relevant Comparator signals regarding Boundary-scan are shown in
Boundary-scan cell from
described in
The Comparator need not be used for pure connectivity testing, since all analog inputs are
shared with a digital port pin as well.
Enable signal
EXTCLKEN
OSCON
RCOSCEN
OSC32EN
TOSKON
From Digital Logic
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock
summaries the scan registers for the external clock pin XTAL1, oscillators with
the Internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is
preferred.
configuration is considered fixed for a given application. The user is advised to scan the same
clock option as to be used in the final system. The enable signals are supported in the scan
chain because the system logic can disable clock options in sleep modes, thereby disconnect-
ing the Oscillator pins from the scan path if not provided. The INTCAP fuses are not supported
in the scan-chain, so the boundary scan chain can not make a XTAL Oscillator requiring inter-
nal capacitors to run unless the fuse is correctly programmed.
Table
Previous
From
Cell
Scanned Clock
Line
EXTCLK (XTAL1)
OSCCK
RCCK
OSC32CK
TOSCK
ShiftDR
103.
0
1
ClockDR
D
Figure 130
UpdateDR
Q
Next
Cell
To
D
G
Q
Clock Option
External Clock
External Crystal
External Ceramic Resonator
External RC
Low Freq. External Crystal
32kHz Timer Oscillator
is attached to each of these signals. The signals are
EXTEST
0
1
XTAL1/TOSC1
(1)(2)(3)
ENABLE
Oscillator
XTAL2/TOSC2
OUTPUT
Previous
From
Cell
Scanned Clock Line
when not Used
ShiftDR
0
1
ClockDR
ATmega128
D
FF1
0
0
1
0
0
Q
next
cell
To
Figure
To System Logic
129. The
259