ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 147

• Manufacturer Part Number: ATMEGA128-16MN
• Description: MCU AVR 128KB FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Compare
Unit
2467V–AVR–02/11
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clk
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR2). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the output compare output
OC2. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page
The Timer/Counter overflow (TOV2) flag is set according to the mode of operation selected by
the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the
output compare flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1 and global inter-
rupt flag in SREG is set), the output compare flag generates an output compare interrupt. The
OCF2 flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 flag
can be cleared by software by writing a logical one to its I/O bit location. The waveform genera-
tor uses the match signal to generate an output according to operating mode set by the
WGM21:0 bits and compare output mode (COM21:0) bits. The max and bottom signals are used
by the waveform generator for handling the special cases of the extreme values in some modes
of operation (see “Modes of Operation” on page 149).
output compare unit.
Figure 63. Output Compare Unit, Block Diagram
The OCR2 Register is double buffered when using any of the pulse width modulation (PWM)
modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-
bottom
T2
Signalize that TCNT2 has reached minimum value (zero).
is present or not. A CPU write overrides (has priority over) all counter clear or
T2
bottom
FOCn
). clk
top
149.
T2
can be generated from an external or internal clock source,
Waveform Generator
WGMn1:0
OCRn
=
(8-bit Comparator )
DATA BUS
COMn1:0
TCNTn
Figure 63
OCFn (Int.Req.)
OCn
shows a block diagram of the
ATmega128
147