ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 84

• Manufacturer Part Number: ATMEGA128-16MN
• Description: MCU AVR 128KB FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Alternate Functions of
Port G
84
ATmega128
In Atmel
Port G, and Port G cannot be used as General Digital Port Pins. The alternate pin configuration
is as follows:
Table 45. Port G Pins Alternate Functions
• TOSC1 – Port G, Bit 4
TOSC1, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous
clocking of Timer/Counter0, pin PG4 is disconnected from the port, and becomes the input of the
inverting Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and the
pin can not be used as an I/O pin.
• TOSC2 – Port G, Bit 3
TOSC2, Timer Oscillator pin 2: When the AS0 bit in ASSR is set (one) to enable asynchronous
clocking of Timer/Counter0, pin PG3 is disconnected from the port, and becomes the inverting
output of the Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and
the pin can not be used as an I/O pin.
• ALE – Port G, Bit 2
ALE is the external data memory Address Latch Enable signal.
• RD – Port G, Bit 1
RD is the external data memory read control strobe.
• WR – Port G, Bit 0
WR is the external data memory write control strobe.
Table 46
Figure 33 on page
Table 46. Overriding Signals for Alternate Functions in PG4..PG1
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Port Pin
PG4
PG3
PG2
PG1
PG0
®
and
AVR
Table 47
®
ATmega103 compatibility mode, only the alternate functions are the defaults for
Alternate Function
TOSC1 (RTC Oscillator Timer/Counter0)
TOSC2 (RTC Oscillator Timer/Counter0)
ALE (Address Latch Enable to external memory)
RD (Read strobe to external memory)
WR (Write strobe to external memory)
PG4/TOSC1
AS0
0
AS0
0
0
0
AS0
0
–
T/C0 OSC INPUT
70.
relates the alternate functions of Port G to the overriding signals shown in
PG3/TOSC2
AS0
0
AS0
0
0
0
AS0
0
–
T/C0 OSC OUTPUT
PG2/ALE
SRE
0
SRE
1
SRE
ALE
0
0
–
–
PG1/RD
SRE
0
SRE
1
SRE
RD
0
0
–
–
2467V–AVR–02/11