MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 51

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908LD64
Freescale Semiconductor
Addr.
$003C
$003D
$003E
$003F
$0040
$0041
$0042
$0043
$0044
$0045
Sync Processor I/O Control
H & V Sync Output Control
ADC Input Clock Register
Vertical Frequency High
Sync Processor Control
Vertical Frequency Low
Hsync Frequency High
Hsync Frequency Low
Register Name
and Status Register
ADC Data Register
Unimplemented
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 15)
—
(SPIOCR)
(ADICLK)
(HVOCR)
Rev. 3.0
(SPCSR)
Register
Register
Register
Register
Register
Register
(HFHR)
(VFHR)
(HFLR)
(VFLR)
(ADR)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read: HOVER
Write:
Read: VSYNCS HSYNCS
Write:
Write:
Write:
Write:
X = Indeterminate
ADIV2
HFH7
VSIE
Bit 7
AD7
VOF
VF7
0
0
0
0
0
0
0
VEDGE
ADIV1
CPW1
HFH6
AD6
VF6
6
0
0
0
0
0
0
0
0
0
Memory Map
COINV
ADIV0
CPW0
HFH5
VSIF
AD5
VF5
5
0
0
0
0
0
0
0
0
0
0
Indeterminate after reset
DCLKPH1 DCLKPH0
= Unimplemented
COMP
HFH4
HFL4
VF12
AD4
VF4
R
4
0
0
0
0
0
0
0
0
VINVO
HFH3
HFL3
VF11
AD3
VF3
R
3
0
0
0
0
0
0
0
0
HINVO
HFH2
VF10
HFL2
AD2
VF2
Input/Output (I/O) Section
R
R
R
2
0
0
0
0
0
0
0
= Reserved
HVOCR1 HVOCR0
BPOR
VPOL
HFH1
HFL1
AD1
VF9
VF1
1
0
0
0
0
0
0
0
0
0
Memory Map
Data Sheet
HPOL
SOUT
HFH0
HFL0
Bit 0
AD0
VF8
VF0
0
0
0
0
0
0
0
0
0
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