MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 230

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Multi-Master IIC Interface (MMIIC)
15.5.5 Multi-Master IIC Data Transmit Register (MMDTR)
Data Sheet
230
Address:
MMTXBE — Multi-Master Transmit Buffer Empty
MMRXBF — Multi-Master Receive Buffer Full
When the MMIIC module is enabled, MMEN = 1, data written into this
register depends on whether module is in master or slave mode.
In slave mode, the data in MMDTR will be transferred to the output circuit
when:
Reset:
Read:
Write:
Figure 15-6. Multi-Master IIC Data Transmit Register (MMDTR)
This flag indicates the status of the data transmit register (MMDTR).
When the CPU writes the data to the MMDTR, the MMTXBE flag will
be cleared. MMTXBE is set when MMDTR is emptied by a transfer of
its data to the output circuit. Reset sets this bit.
This flag indicates the status of the data receive register (MMDRR).
When the CPU reads the data from the MMDRR, the MMRXBF flag
will be cleared. MMRXBF is set when MMDRR is full by a transfer of
data from the input circuit to the MMDRR. Reset clears this bit.
•
•
1 = Data transmit register empty
0 = Data transmit register full
1 = Data receive register full
0 = Data receive register empty
the module detects a matched calling address (MMATCH = 1),
with the calling master requesting data (MMSRW = 1); or
the previous data in the output circuit has be transmitted and the
receiving master returns an acknowledge bit, indicated by a
received acknowledge bit (MMRXAK = 0).
MMTD7
$006E
Bit 7
Multi-Master IIC Interface (MMIIC)
1
MMTD6
6
1
MMTD5
5
1
MMTD4
4
1
MMTD3
3
1
MC68HC908LD64
MMTD2
Freescale Semiconductor
2
1
MMTD1
1
1
—
MMTD0
Rev. 3.0
Bit 0
1