MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 266

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Sync Processor
Data Sheet
266
HFH[7:0], HFL[4:0] — Horizontal Line Frequency
HOVER — Hsync Frequency Counter Overflow
This read-only 13-bit contains the number of horizontal lines in a
32ms window. An internal 13-bit counter counts the Hsync pulses
within a 32ms window in every 32.768ms period. If the FSHF bit in
SPCR1 is set, only the most 11-bits (HFH[7:0] & HFL[4:2]) will be
updated by the counter. Thus, providing a Hsync pulse count in a 8ms
window in every 8.192ms.
The most significant 8 bits of counted value is transferred to the high
byte register, and the least significant 5 bits is transferred to an
intermediate buffer. When the high byte register is read, the 5-bit
counted value stored in the intermediate buffer will be uploaded to the
low byte register. Therefore, user the program must read the high byte
register first then low byte register in order to get the complete
counted value of Hsync pulses. If the counter overflows, the overflow
flag, HOVER, will be set, indicating the number of Hsync pulses in
32ms are more than 8191 (2
than 256kHz.
For the 32ms window, the HFHR and HFLR are such that the
frequency step unit in the 5-bit of HFLR is 0.03125kHz, and the step
unit in the 8-bit HFHR is 1kHz. Therefore, the Hsync frequency can
be easily calculated by:
This read-only bit is set when an overflow has occurred on the 13-bit
Hsync frequency counter. Reset clears this bit, and will be updated
every count period.
An overflow occurs when the number Hsync pulses exceed 8191, a
Hsync frequency greater than 256kHz.
1 = A Hsync frequency counter overflow has occurred
0 = No Hsync frequency counter overflow has occurred
Hsync Frequency = [HFH + (HFL × 0.03125)] kHz
where: HFH is the value of HFH[7:0]
Sync Processor
HFL is the value of HFL[4:0]
13
–1), i.e. a Hsync frequency greater
MC68HC908LD64
Freescale Semiconductor
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Rev. 3.0