MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 246

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

DDC12AB Interface
16.6.6 DDC Data Transmit Register (DDCDTR)
Data Sheet
246
Address:
RXBF — DDC Receive Buffer Full
When the DDC module is enabled, DEN = 1, data written into this
register depends on whether module is in master or slave mode.
In slave mode, the data in DDCDTR will be transferred to the output
circuit when:
If the calling master does not return an acknowledge bit (RXAK = 1), the
module will release the SDA line for master to generate a "stop" or
"repeated start" condition. The data in the DDCDTR will not be
transferred to the output circuit until the next calling from a master. The
transmit buffer empty flag remains cleared (TXBE = 0).
In master mode, the data in DDCDTR will be transferred to the output
circuit when:
Reset:
Read:
Write:
This flag indicates the status of the data receive register (DDCDRR).
When the CPU reads the data from the DDCDRR, the RXBF flag will
be cleared. RXBF is set when DDCDRR is full by a transfer of data
from the input circuit to the DDCDRR. Reset clears this bit.
•
•
1 = Data receive register full
0 = Data receive register empty
the module detects a matched calling address (MATCH = 1), with
the calling master requesting data (SRW = 1); or
the previous data in the output circuit has be transmitted and the
receiving master returns an acknowledge bit, indicated by a
received acknowledge bit (RXAK = 0).
Figure 16-7. DDC Data Transmit Register (DDCDTR)
$001A
DTD7
Bit 7
1
DDC12AB Interface
DTD6
6
1
DTD5
5
1
DTD4
4
1
DTD3
3
1
MC68HC908LD64
DTD2
Freescale Semiconductor
2
1
DTD1
1
1
—
Rev. 3.0
DTD0
Bit 0
1