MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 244

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

DDC12AB Interface
16.6.5 DDC Status Register (DDCSR)
Data Sheet
244
Address:
RXIF — DDC Receive Interrupt Flag
TXIF — DDC Transmit Interrupt Flag
MATCH — DDC Address Match
Reset:
Read:
Write:
This flag is set after the data receive register (DDCDRR) is loaded
with a new received data. Once the DDCDRR is loaded with received
data, no more received data can be loaded to the DDCDRR until the
CPU reads the data from the DDCDRR to clear RXBF flag. RXIF
generates an interrupt request to CPU if the DIEN bit in DDCCR is
also set. This bit is cleared by writing "0" to it or by reset; or when the
DEN = 0.
This flag is set when data in the data transmit register (DDCDTR) is
downloaded to the output circuit, and that new data can be written to
the DDCDTR. TXIF generates an interrupt request to CPU if the DIEN
bit in DDCCR is also set. This bit is cleared by writing "0" to it or when
the DEN = 0.
This flag is set when the received data in the data receive register
(DDCDRR) is a calling address which matches with the address or its
extended addresses (EXTAD=1) specified in the DDCADR register.
1 = New data in data receive register (DDCDRR)
0 = No data received
1 = Data transfer completed
0 = Data transfer in progress
1 = Received address matches DDCADR
0 = Received address does not match
$0019
RXIF
Bit 7
0
0
Figure 16-6. DDC Status Register (DDCSR)
= Unimplemented
DDC12AB Interface
TXIF
6
0
0
MATCH
5
0
SRW
4
0
RXAK
3
1
MC68HC908LD64
SCLIF
Freescale Semiconductor
2
0
0
TXBE
1
1
—
Rev. 3.0
RXBF
Bit 0
0