MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 225

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.5.2 Multi-Master IIC Control Register (MMCR)
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
Address:
MMEN — Multi-Master IIC Enable
MMIEN — Multi-Master IIC Interrupt Enable
MMTXAK — Transmit Acknowledge Enable
Reset:
Read:
Write:
This bit is set to enable the Multi-master IIC module. When
MMEN = 0, module is disabled and all flags will restore to its power-
on default states. Reset clears this bit.
When this bit is set, the MMTXIF, MMRXIF, MMALIF, and MMNAKIF
flags are enabled to generate an interrupt request to the CPU. When
MMIEN is cleared, the these flags are prevented from generating an
interrupt request. Reset clears this bit.
This bit is set to disable the MMIIC from sending out an acknowledge
signal to the bus at the 9th clock bit after receiving 8 data bits. When
MMTXAK is cleared, an acknowledge signal will be sent at the 9th
clock bit. Reset clears this bit.
1 = MMIIC module enabled
0 = MMIIC module disabled
1 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will
0 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will not
1 = MMIIC does not send acknowledge signals at 9th clock bit
0 = MMIIC sends acknowledge signal at 9th clock bit
Figure 15-3. Multi-Master IIC Control Register (MMCR)
MMEN
$006C
Bit 7
generate interrupt request to CPU
generate interrupt request to CPU
Multi-Master IIC Interface (MMIIC)
0
= Unimplemented
MMIEN
6
0
5
0
0
4
0
0
MMTXAK
3
0
Multi-Master IIC Interface (MMIIC)
Multi-Master IIC Registers
2
0
0
1
0
0
Data Sheet
Bit 0
0
0
225