MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 226

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Multi-Master IIC Interface (MMIIC)
15.5.3 Multi-Master IIC Master Control Register (MIMCR)
Data Sheet
226
Address:
MMALIF — Multi-Master Arbitration Lost Interrupt Flag
MMNAKIF — No Acknowledge Interrupt Flag
MMBB — Bus Busy Flag
Reset:
Figure 15-4. Multi-Master IIC Master Control Register (MIMCR)
Read: MMALIF MMNAKIF
Write:
This flag is set when software attempt to set MMAST but the MMBB
has been set by detecting the start condition on the lines or when the
MMIIC is transmitting a "1" to SDA line but detected a "0" from SDA
line in master mode – an arbitration loss. This bit generates an
interrupt request to the CPU if the MMIEN bit in MMCR is also set.
This bit is cleared by writing "0" to it or by reset.
This flag is only set in master mode (MMAST = 1) when there is no
acknowledge bit detected after one data byte or calling address is
transferred. This flag also clears MMAST. MMNAKIF generates an
interrupt request to CPU if the MMIEN bit in MMCR is also set. This
bit is cleared by writing "0" to it or by reset.
This flag is set after a start condition is detected (bus busy), and is
cleared when a stop condition (bus idle) is detected or the MMIIC is
disabled. Reset clears this bit.
1 = Lost arbitration in master mode
0 = No arbitration lost
1 = No acknowledge bit detected
0 = Acknowledge bit detected
1 = Start condition detected
0 = Stop condition detected or MMIIC is disabled
$006A
Bit 7
Multi-Master IIC Interface (MMIIC)
0
0
6
0
0
MMBB
5
0
MMAST
4
0
MMRW
3
0
MC68HC908LD64
MMBR2
Freescale Semiconductor
2
0
MMBR1
1
0
—
MMBR0
Rev. 3.0
Bit 0
0