MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 260

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Sync Processor
Data Sheet
260
VEDGE — VSync Interrupt Edge Select
VSIF — VSync Interrupt Flag
COMP — Composite Sync Input Enable
VINVO — VOUT Signal Polarity
HINVO — HOUT Signal Polarity
This bit specifies the triggering edge of Vsync interrupt. When it is "0",
the rising edge of internal Vsync signal which is either from the
VSYNC pin or extracted from the composite input signal will set VSIF
flag. When it is "1", the falling edge of internal Vsync signal will set
VSIF flag. Reset clears this bit.
This flag is only set by the specified edge of the internal Vsync signal,
which is either from the VSYNC input pin or extracted from the
composite sync input signal. The triggering edge is specified by the
VEDGE bit. VSIF generates an interrupt request to the CPU if the
VSIE bit is also set. This bit is cleared by writing a "0" to it or by a reset.
This bit is set to enable the separator circuit which extracts the Vsync
pulse from the composite sync input on HSYNC. The extracted Vsync
signal is used as it were from the VSYNC input. Reset clears this bit.
This bit, together with the ATPOL bit in SPCR1 controls the output
polarity of the VOUT signal (see
This bit, together with the ATPOL bit in SPCR1 controls the output
polarity of the HOUT signal (see
1 = VSIF bit will be set by falling edge of Vsync
0 = VSIF bit will be set by rising edge of Vsync
1 = A valid edge is detected on the Vsync
0 = No valid Vsync is detected
1 = Composite sync input enabled
0 = Composite sync input disabled
Sync Processor
Table
Table
17-4).
17-4).
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0