MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 245

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
SRW — DDC Slave Read/Write
RXAK — DDC Receive Acknowledge
SCLIF — SCL Interrupt Flag
TXBE — DDC Transmit Buffer Empty
This bit indicates the data direction when the module is in slave mode.
It is updated after the calling address is received from a master
device. SRW = 1 when the calling master is reading data from the
module (slave transmit mode). SRW = 0 when the master is writing
data to the module (receive mode).
When this bit is cleared, it indicates an acknowledge signal has been
received after the completion of 8 data bits transmission on the bus.
When RXAK is set, it indicates no acknowledge signal has been
detected at the 9th clock; the module will release the SDA line for the
master to generate "stop" or "repeated start" condition. Reset sets this
bit.
This flag is set when a falling edge is detected on the SCL line, only if
DDC1EN bit is set. SCLIF generates an interrupt request to CPU if the
SCLIEN bit in DDCCR is also set. SCLIF is cleared by writing "0" to it
or when the DCC1EN = 0, or DEN = 0. Reset clears this bit.
This flag indicates the status of the data transmit register (DDCDTR).
When the CPU writes the data to the DDCDTR, the TXBE flag will be
cleared. TXBE is set when DDCDTR is emptied by a transfer of its
data to the output circuit. Reset sets this bit.
1 = Slave mode transmit
0 = Slave mode receive
1 = No acknowledge signal received at 9th clock bit
0 = Acknowledge signal received at 9th clock bit
1 = Falling edge detected on SCL line
0 = No falling edge detected on SCL line
1 = Data transmit register empty
0 = Data transmit register full
DDC12AB Interface
DDC12AB Interface
DDC Registers
Data Sheet
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