MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 263

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

17.6.3 Vertical Frequency Registers (VFRs)
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
Address:
Address:
This register pair contains the 13-bit vertical frequency count value, an
overflow bit, and the clamp pulse width selection bits.
VF[12:0] — Vertical Frame Frequency
Reset:
Reset:
Read:
Read:
Write:
Write:
This read-only 13-bit contains information of the vertical frame
frequency. An internal 13-bit counter counts the number of 8µs
periods between two Vsync pulses. The most significant 5 bits of the
counted value is transferred to the high byte register, and the least
significant 8 bits is transferred to an intermediate buffer. When the
high byte register is read, the 8-bit counted value stored in the
intermediate buffer will be uploaded to the low byte register.
Therefore, user program must read the high byte register first, then
low byte register in order to get the complete counted value of one
vertical frame. If the counter overflows, the overflow flag, VOF, will be
set, indicating the counter value stored in the VFRs is meaningless.
The data corresponds to the period of one vertical frame. This register
can be read to determine if the frame frequency is valid, and to
determine the video mode.
$0041
$0042
Bit 7
VOF
Bit 7
VF7
0
0
Figure 17-6. Vertical Frequency High Register
Figure 17-7. Vertical Frequency Low Register
= Unimplemented
CPW1
VF6
Sync Processor
6
0
0
6
0
CPW0
VF5
5
0
0
5
0
VF12
VF4
4
0
4
0
VF11
VF3
3
0
3
0
Sync Processor I/O Registers
VF10
VF2
2
0
2
0
VF9
VF1
Sync Processor
1
0
1
0
Data Sheet
Bit 0
Bit 0
VF8
VF0
0
0
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