MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 241

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.6.4 DDC Master Control Register (DDCMCR)
MC68HC908LD64
Freescale Semiconductor
—
Rev. 3.0
Address:
SCLIEN — SCL Interrupt Enable
DDC1EN — DDC1 Protocol Enable
ALIF — DDC Arbitration Lost Interrupt Flag
Reset:
Read:
Write:
When this bit is set, the SCLIF flag is enabled to generate an interrupt
request to the CPU. When SCLIEN is cleared, SCLIF is prevented
from generating an interrupt request. Reset clears this bit.
This bit is set to enable DDC1 protocol. The DDC1 protocol will use
the Vsync input (from sync processor) as the master clock input to the
DDC module. Vsync rising-edge will continuously clock out the data
to the output circuit. No calling address comparison is performed. The
SRW bit in DDC status register (DDCSR) will always read as "1".
Reset clears this bit.
This flag is set when software attempt to set MAST but the BB has
been set by detecting the start condition on the lines or when the DDC
is transmitting a "1" to SDA line but detected a "0" from SDA line in
master mode – an arbitration loss. This bit generates an interrupt
request to the CPU if the DIEN bit in DDCCR is also set. This bit is
cleared by writing "0" to it or by reset.
1 = SCLIF bit set will generate interrupt request to CPU
0 = SCLIF bit set will not generate interrupt request to CPU
1 = DDC1 protocol enabled
0 = DDC1 protocol disabled
1 = Lost arbitration in master mode
0 = No arbitration lost
Figure 16-5. DDC Master Control Register (DDCMCR)
$0016
ALIF
Bit 7
0
0
DDC12AB Interface
NAKIF
6
0
0
BB
5
0
MAST
4
0
MRW
3
0
BR2
2
0
DDC12AB Interface
BR1
1
0
DDC Registers
Data Sheet
Bit 0
BR0
0
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