MC908LD64IFUE Freescale Semiconductor, MC908LD64IFUE Datasheet - Page 100

• Manufacturer Part Number: MC908LD64IFUE
• Description: IC MCU 8BIT FOR LCD 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LD64IFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: I²C, USB
• Peripherals: OSD, POR, PWM
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08LD
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, USB
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Clock Generator Module (CGM)
8.2 Introduction
8.3 Features
8.4 Functional Description
Data Sheet
100
This section describes the clock generator module (CGM). Using the
crystal reference clock from the oscillator module, the CGM generates
the display base clock, DCLK1, for the sync processor module. The
CGM is able to generate a frequency up to 108MHz from a 24MHz
reference clock.
Features of the CGM include the following:
The CGM consists of three major sub-modules:
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Phase-locked loop with output frequency in integer multiples of the
crystal reference
Programmable hardware voltage-controlled oscillator (VCO) for
low-jitter operation
Automatic bandwidth control mode for low-jitter operation
Automatic frequency lock detector
CPU interrupt on entry or exit from locked condition
Crystal oscillator circuit which generates the buffered constant
crystal frequency clock, OSCRCLK. (See
(OSC).)
Phase-locked loop (PLL) which generates the programmable
VCO frequency clock CGMVCLK.
Base clock selector circuit; this software-controlled circuit selects
either OSCXCLK divided by two or the VCO clock CGMVCLK
divided by two, as the base clock DCLK1. The sync processor
derives other display clocks from DCLK1.
Clock Generator Module (CGM)
MC68HC908LD64
Section 7. Oscillator
Freescale Semiconductor
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Rev. 3.0