AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 833

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.6.7.2
30.6.8
30.6.8.1
30.6.8.2
Figure 30-13. SR.XFRDONE During a Read Access
32072G–11/2011
MCI Transfer Done Timings
Definition
Read Access
Boot Procedure, dma mode
XFRDONE flag
CMDRDY flag
Not busy flag
CMD line
Data
The SR.XFRDONE bit indicates exactly when the read or write sequence is finished.
During a read access, the SR.XFRDONE bit behaves as shown in
5. Host processor can copy boot data sequentialy as soon as the RXRDY flag is asserted.
6. When Data transfer is completed, host processor shall terminate the boot stream by
1. Configure MCI2 data bus width programming SDCBUS Field in the MCI_SDCR regis-
2. Set the bytecount to 512 bytes and the blockcount to the desired number of block, writ-
3. Enable DMA transfer in the MCI_DMA register.
4. Configure DMA controller, program the total amount of data to be transferred and
5. Issue the Boot Operation Request command by writing to the MCI_CMDR register with
6. DMA controller copies the boot partition to the memory.
7. When DMA transfer is completed, host processor shall terminate the boot stream by
MCI read CMD
writing the MCI_CMDR register with SPCMD field set to BOOTEND.
ter. The BOOT_BUS_WIDTH field in the device Extended CSD register must be set
accordingly.
ing BLKLEN and BCNT fields of the MCI_BLKR Register.
enable the relevant channel.
SPCND set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”.
writing the MCI_CMDR register with SPCMD field set to BOOTEND.
Card response
1st Block
The CMDRDY flag is released 8 t
Last Block
bit
lafter the end of the card response.
Figure 30-13 on page
833.
833