AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 667

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

• FRZCLK: Freeze USB Clock
• VBUSPO: VBus Polarity
• OTGPADE: OTG Pad Enable
• VBUSHWC: VBus Hardware Control
• STOE: Suspend Time-Out Interrupt Enable
• ROLEEXE: Role Exchange Interrupt Enable
• BCERRE: B-Connection Error Interrupt Enable
• VBERRE: VBus Error Interrupt Enable
• VBUSTE: VBus Transition Interrupt Enable
• IDTE: ID Transition Interrupt Enable
32072G–11/2011
This bit can be written even if FRZCLK is one.
1: The clock input are disabled (the resume detection is still active).This reduces power consumption. Unless explicitly stated,
all registers then become read-only.
0: The clock inputs are enabled.
This bit can be written even if USBE is zero. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit, but
this freezes the clock inputs whatever its value.
1: The USB_VBOF output signal is inverted (active low).
0: The USB_VBOF output signal is in its default mode (active high).
To be generic. May be useful to control an external VBus power module.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
1: The OTG pad is enabled.
0: The OTG pad is disabled.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
1: The hardware control over the USB_VBOF output pin is disabled.
0: The hardware control over the USB_VBOF output pin is enabled. The USBB resets the USB_VBOF output pin when a VBUS
problem occurs.
1: The Suspend Time-Out Interrupt (STOI) is enabled.
0: The Suspend Time-Out Interrupt (STOI) is disabled.
1: The Role Exchange Interrupt (ROLEEXI) is enabled.
0: The Role Exchange Interrupt (ROLEEXI) is disabled.
1: The B-Connection Error Interrupt (BCERRI) is enabled.
0: The B-Connection Error Interrupt (BCERRI) is disabled.
1: The VBus Error Interrupt (VBERRI) is enabled.
0: The VBus Error Interrupt (VBERRI) is disabled.
1: The VBus Transition Interrupt (VBUSTI) is enabled.
0: The VBus Transition Interrupt (VBUSTI) is disabled.
1: The ID Transition interrupt (IDTI) is enabled.
0: The ID Transition interrupt (IDTI) is disabled.
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