AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 829

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.6.4.1
30.6.4.2
30.6.4.3
32072G–11/2011
WRITE_MULTIPLE_BLOCK
WRITE_SINGLE_BLOCK operation using DMA Controller
READ_SINGLE_BLOCK operation using DMA Controller
1. Wait until the current command execution has successfully terminated.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Configure the DMA Channel in the DMA Controller.
5. Write the DMA register with the following fields:
6. Write a one to the DMA Transfer done bit in IER register (IER.DMADONE).
7. Issue a WRITE_SINGLE_BLOCK command.
8. Wait for DMA Transfer done bit in SR register (SR.DMADONE) is set.
1. Wait until the current command execution has successfully terminated.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Configure the DMA Channel in the DMA Controller.
5. Write the DMA register with the following fields:
6. Write a one to the IER.DMADONE bit.
7. Issue a READ_SINGLE_BLOCK command.
8. Wait for SR.DMADONE bit is set.
1. Wait until the current command execution has successfully terminated.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Program the DMA Controller to use a list of descriptors. Each descriptor transfers one
5. Program the DMA register with the following fields:
6. Write a one to the IER.DMADONE bit.
7. Issue a WRITE_MULTIPLE_BLOCK command.
8. Wait for DMA chained buffer transfer complete interrupt.
c. Check that the Transfer Done bit in the SR register (SR.XFRDONE) is set
– Write the dma_offset to the DMA Write Buffer Offset field (DMA.OFFSET).
– Write the DMA Channel Read and Write Chunk Size field (DMA.CHKSIZE).
– Write a one to he DMA.DMAEN bit to enable DMA hardware handshaking in the
d. Check that the SR.XFRDONE bit is set.
– Write zero to the DMA.OFFSET field.
– Write the DMA.CHKSIZE field.
– Write to one the DMA.DMAEN bit to enable DMA hardware handshaking in the MCI.
a. Check that the SR.XFRDONE bit is set.
block of data.
– Write the dma_offset in the DMA.OFFSET field.
– Write the DMA.CHKSIZE field.
– Write a one to the DMA.DMAEN bit to enable DMA hardware handshaking in the
MCI.
MCI.
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