AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 180

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 15-3.
15.6.3
15.6.3.1
15.6.3.2
32072G–11/2011
Connection to External Devices
SMC
Data bus width
Byte write or byte select access
Memory Connections for Six External Devices
NCS[0] - NCS[5]
A[AD_MSB:0]
D[15:0]
NWE
NRD
A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by
the Data Bus Width field in the Mode Register (MODE.DBW) for the corresponding chip select.
Figure 15-4 on page 180
page 181
Each chip select with a 16-bit data bus can operate with one of two different types of write
access: byte write or byte select access. This is controlled by the Byte Access Type bit in the
MODE register (MODE.BAT) for the corresponding chip select.
Figure 15-4.
shows how to connect a 512K x 16-bit memory on NCS2.
Memory Connection for an 8-bit Data Bus
SMC
shows how to connect a 512K x 8-bit memory on NCS2.
NCS[2]
A[18:2]
D[7:0]
NWE
NRD
A0
A1
8 or 16
NCS0
NCS1
NCS2
A[AD_MSB:0]
D[15:0] or D[7:0]
Memory Enable
Output Enable
Write Enable
NCS3
Memory Enable
NCS4
Memory Enable
NCS5
Memory Enable
D[7:0]
A[18:2]
Write Enable
Output Enable
Memory Enable
A0
A1
Memory Enable
Memory Enable
Figure 15-5 on
180