AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 335

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
Figure 19-11. Multi-Block DMA Transfer with Source and Destination Address Auto-reloaded
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
block in the DMA transfer, then the block complete ISR (interrupt service routine)
should clear the reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS
registers. This put the DMACA into Row 1 as shown in
the next block is not the last block in the DMA transfer, then the reload bits should
remain enabled to keep the DMACA in Row 4.
masked (MaskBlock[x] = 1’b0, where x is the channel number), then hardware
does not stall until it detects a write to the block complete interrupt clear register but
starts the next block transfer immediately. In this case software must clear the
reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers to put the
DMACA into ROW 1 of
transfer has completed. The transfer is similar to that shown in
page
Source Layer
Address of
335. The DMA transfer flow is shown in
SAR
Source Blocks
Table 19-1 on page 326
Block2
Block0
Block1
BlockN
Destination Blocks
Figure 19-12 on page
before the last block of the DMA
Table 19-1 on page
Destination Layer
DAR
Address of
Figure 19-11 on
336.
326. If
335