AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 649

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.7.3.11
32072G–11/2011
RXINI
FIFOCON
IN
Management of OUT pipes
(bank 0)
DATA
RXINI
FIFOCON
RXINI shall be cleared by software (by writing a one to the Received IN Data Interrupt Clear bit
in the Pipe n Control Clear register(UPCONnCLR.RXINIC)) to acknowledge the interrupt, what
has no effect on the pipe FIFO.
The user then reads from the FIFO (see
DATA)” on page
(FIFOCONC) bit in UPCONnCLR) to free the bank. If the IN pipe is composed of multiple banks,
this also switches to the next bank. The RXINI and FIFOCON bits are updated in accordance
with the status of the next bank.
RXINI shall always be cleared before clearing FIFOCON.
The Read/Write Allowed (RWALL) bit in UPSTAn is set when the current bank is not empty, i.e.,
the software can read further data from the FIFO.
Figure 26-24. Example of an IN Pipe with 1 Data Bank
Figure 26-25. Example of an IN Pipe with 2 Data Banks
OUT packets are sent by the host. All the data can be written which acknowledges or not the
bank when it is full.
The pipe must be configured and unfrozen first.
IN
ACK
HW
(bank 0)
DATA
SW
740) and clears the FIFOCON bit (by writing a one to the FIFO Control Clear
read data from CPU
BANK 0
ACK
HW
SW
SW
read data from CPU
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
IN
BANK 0
IN
(bank 1)
DATA
(bank 0)
DATA
SW
ACK
HW
ACK
HW
read data from CPU
read data from CPU
SW
SW
BANK 1
BANK 0
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