AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 226

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 16-6. Read Burst with Boundary Row Access
16.7.5
32072G–11/2011
SDRAMC_A[12:0]
D[15:0]
SDWE
SDCS
SDCK
RAS
CAS
SDRAM Controller Refresh Cycles
Col a
Row n
Col b
Dna
An auto refresh command is used to refresh the SDRAM device. Refresh addresses are gener-
ated internally by the SDRAM device and incremented after each auto refresh automatically.
The SDRAMC generates these auto refresh commands periodically. An internal timer is loaded
with the value in the Refresh Timer Register (TR) that indicates the number of clock cycles
between successive refresh cycles.
A refresh error interrupt is generated when the previous auto refresh command did not perform.
In this case a Refresh Error Status bit is set in the Interrupt Status Register (ISR.RES). It is
cleared by reading the ISR register.
When the SDRAMC initiates a refresh of the SDRAM device, internal memory accesses are not
delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the device is
busy and the master is held by a wait signal. See
Col c
Dnb
Col d
Dnc
Dnd
T
RP
= 3
Row m
T
RCD
= 3
Figure 16-7 on page
Col a
CAS = 2
Col b
Dma
Col c
227.
Dmb
Col d
Dmc
Col e
Dmd
Dme
226