AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 345

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 19-19. DMA Transfer Flow for Source Address Auto-reloaded and Contiguous Destination Address
19.11 Disabling a Channel Prior to Transfer Completion
32072G–11/2011
Under normal operation, software enables a channel by writing a ‘1’ to the Channel Enable Reg-
ister, ChEnReg.CH_EN, and hardware disables a channel on transfer completion by clearing the
ChEnReg.CH_EN register bit.
The recommended way for software to disable a channel without losing data is to use the
CH_SUSP bit in conjunction with the FIFO_EMPTY bit in the Channel Configuration Register
(CFGx) register.
1. If software wishes to disable a channel prior to the DMA transfer completion, then it can
2. Software can now poll the CFGx.FIFO_EMPTY bit until it indicates that the channel
Block Complete interrupt
DMAC Transfer Complete
interrupt generated here
set the CFGx.CH_SUSP bit to tell the DMACA to halt all transfers from the source
peripheral. Therefore, the channel FIFO receives no new data.
FIFO is empty.
generated here
Hardware reprograms
DMAC block transfer
Channel Enabled by
Source/destination
Row 1 of Table 4 ?
Channel Disabled by
SARx, CTLx, LLPx
Is DMAC in
status fetch
LLI Fetch
software
hardware
yes
no
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