AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 660

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 26-4.
32072G–11/2011
0x031C
0x032C
0x033C
0x034C
0x035C
0x036C
0x0320
0x0324
0x0328
0x0330
0x0334
0x0338
0x0340
0x0344
0x0348
0x0350
0x0354
0x0358
0x0360
0x0364
0x0368
0x0370
Offset
USBB Register Memory Map
Device DMA Channel 2 HSB Address Register
Device DMA Channel 3 HSB Address Register
Device DMA Channel 4 HSB Address Register
Device DMA Channel 5 HSB Address Register
Device DMA Channel 6 HSB Address Register
Device DMA Channel 2 Control Register
Device DMA Channel 3 Control Register
Device DMA Channel 4 Control Register
Device DMA Channel 5 Control Register
Device DMA Channel 6 Control Register
Device DMA Channel 1 Status Register
Device DMA Channel 2 Next Descriptor
Device DMA Channel 2 Status Register
Device DMA Channel 3 Next Descriptor
Device DMA Channel 3 Status Register
Device DMA Channel 4 Next Descriptor
Device DMA Channel 4 Status Register
Device DMA Channel 5 Next Descriptor
Device DMA Channel 5 Status Register
Device DMA Channel 6 Next Descriptor
Device DMA Channel 6 Status Register
Device DMA Channel 7 Next Descriptor
Address Register
Address Register
Address Register
Address Register
Address Register
Address Register
Register
NEXTDESC
NEXTDESC
NEXTDESC
NEXTDESC
NEXTDESC
NEXTDESC
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
UDDMA1
UDDMA2
UDDMA2
UDDMA2
UDDMA2
UDDMA3
UDDMA3
UDDMA3
UDDMA3
UDDMA4
UDDMA4
UDDMA4
UDDMA4
UDDMA5
UDDMA5
UDDMA5
UDDMA5
UDDMA6
UDDMA6
UDDMA6
UDDMA6
UDDMA7
STATUS
STATUS
STATUS
STATUS
STATUS
STATUS
ADDR
ADDR
ADDR
ADDR
ADDR
Name
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Access
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
660