AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 638

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.7.2.12
32072G–11/2011
Management of IN endpoints
•Overview
TXINI
FIFOCON
IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be written which acknowledges or not the bank when it is full.
The endpoint must be configured first.
The TXINI bit is set at the same time as FIFOCON when the current bank is free. This triggers
an EPnINT interrupt if the Transmitted IN Data Interrupt Enable (TXINE) bit in UECONn is one.
TXINI shall be cleared by software (by writing a one to the Transmitted IN Data Interrupt Enable
Clear bit in the Endpoint n Control Clear register (UECONnCLR.TXINIC)) to acknowledge the
interrupt, what has no effect on the endpoint FIFO.
The user then writes into the FIFO (see
DATA)” on page
UECONnCLR to clear the FIFOCON bit. This allows the USBB to send the data. If the IN end-
point is composed of multiple banks, this also switches to the next bank. The TXINI and
FIFOCON bits are updated in accordance with the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
The RWALL bit is set when the current bank is not full, i.e. the software can write further data
into the FIFO.
Figure 26-16. Example of an IN Endpoint with 1 Data Bank
SW
write data to CPU
NAK
BANK 0
740) and write a one to the FIFO Control Clear (FIFOCONC) bit in
SW
IN
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
(bank 0)
DATA
HW
ACK
SW
write data to CPU
BANK 0
SW
IN
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