AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 507

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24. Synchronous Serial Controller (SSC)
24.1
24.2
32072G–11/2011
Features
Overview
Rev: 3.2.0.2
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The Synchronous Serial Controller (SSC) provides a synchronous communication link with
external devices. It supports many serial synchronous communication protocols generally used
in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc.
The SSC consists of a receiver, a transmitter, and a common clock divider. Both the receiver
and the transmitter interface with three signals:
The transfers can be programmed to start automatically or on different events detected on the
Frame Sync signal.
The SSC’s high-level of programmability and its two dedicated Peripheral DMA Controller chan-
nels of up to 32 bits permit a continuous high bit rate data transfer without processor
intervention.
Featuring connection to two Peripheral DMA Controller channels, the SSC permits interfacing
with low processor overhead to the following:
• the TX_DATA/RX_DATA signal for data
• the TX_CLOCK/RX_CLOCK signal for the clock
• the TX_FRAME_SYNC/RX_FRAME_SYNC signal for the frame synchronization
• CODEC’s in master or slave mode
• DAC through dedicated serial interface, particularly I2S
• Magnetic card reader
Provides serial synchronous communication links used in audio and telecom applications
Independent receiver and transmitter, common clock divider
Interfaced with two Peripheral DMA Controller channels to reduce processor overhead
Configurable frame sync and data length
Receiver and transmitter can be configured to start automatically or on detection of different
events on the frame sync signal
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
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