AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 783

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28. Analog-to-Digital Converter (ADC)
28.1
28.2
32072G–11/2011
Features
Overview
Rev: 2.0.0.1
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The Analog-to-Digital Converter (ADC) is based on a Successive Approximation Register (SAR)
10-bit ADC. It also integrates an 8-to-1 analog multiplexer, making possible the analog-to-digital
conversions of 8 analog lines. The conversions extend from 0V to VDDANA.
The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a
common register for all channels, as well as in a channel-dedicated register. Software trigger,
external trigger on rising edge of the TRIGGER pin, or internal triggers from timer counter out-
put(s) are configurable.
The ADC also integrates a sleep mode and a conversion sequencer and connects with a Periph-
eral DMA Controller channel. These features reduce both power consumption and processor
intervention.
Finally, the user can configure ADC timings, such as startup time and sample & hold time.
Integrated multiplexer offering up to eight independent analog inputs
Individual enable and disable of each channel
Hardware or software trigger
Peripheral DMA Controller support
Possibility of ADC timings configuration
Sleep mode and conversion sequencer
– External trigger pin
– Timer counter outputs (corresponding TIOA trigger)
– Automatic wakeup on trigger and back to sleep mode after conversions of all enabled
channels
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