AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 450

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
The TWI transfers require the receiver to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the mas-
ter to pull it down in order to generate the acknowledge. The slave polls the data line during this
clock pulse and sets the NAK bit in SR if the master does not acknowledge the data byte. A NAK
means that the master does not wish to receive additional data bytes. As with the other status
bits, an interrupt can be generated if enabled in the Interrupt Enable Register (IER).
SR.TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.
The end of the complete transfer is marked by the SR.TCOMP bit changing from zero to one.
See
Figure 22-7. Slave Transmitter with One Data Byte
4. NBYTES is updated. If CR.CUP is one, NBYTES is incremented, otherwise NBYTES is
5. After each data byte has been transmitted, the master transmits an ACK (Acknowl-
6. If STOP is received, SR.TCOMP and SR.STO will be set.
7. If REPEATED START is received, SR.REP will be set.
Figure 22-7
decremented.
edge) or NAK (Not Acknowledge) bit. If a NAK bit is received by the TWIS, the SR.NAK
bit is set. Note that this is done two CLK_TWIS cycles after TWCK has been sampled
by the TWIS to be HIGH (see
ished, and the TWIS will wait for a STOP or REPEATED START. If an ACK bit is
received, the SR.NAK bit remains LOW. The ACK indicates that more data should be
transmitted, jump to step 2. At the end of the ACK/NAK clock cycle, the Byte Transfer
Finished (SR.BTF) bit is set. Note that this is done two CLK_TWIS cycles after TWCK
has been sampled by the TWIS to be LOW (see
event that SR.NAK bit is set, it must not be cleared before the SR.BTF bit is set to
ensure correct TWIS behavior.
TCOMP
TXRDY
TWD
Write THR (DATA)
and
NBYTES set to 1
S
Figure
DADR
22-8.
Figure
R
22-9). The NAK indicates that the transfer is fin-
A
DATA
Figure
22-9). Also note that in the
N
STOP sent by master
P
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