AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 169

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.6.5.3
32072G–11/2011
Read/Write signals
ured to drive 8-bit memory devices on the corresponding NCS pin (NCS[4] or NCS[5]). The Data
Bus Width (DBW) field in the SMC Mode (MODE) register of the NCS[4] and/or NCS[5] address
space must be written as shown in
NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set
in Byte Select mode on the corresponding Chip Select.
The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For
details on these waveforms and timings, refer to the SMC Section.
Table 14-5.
During read operations, in I/O mode, the CompactFlash logic drives the read command signals
of the SMC on CFNIORD signal, while the CFNOE is deactivated. Likewise, in common memory
mode and attribute memory mode, the SMC signals are driven on the CFNOE signal, while the
CFNIORD is deactivated.
this logic.
During write operations, in all modes, the CompactFlash logic drives the write command signal
of the SMC on CFNWE signal. Addtionnal external logic is required to drive _WE and _IOWR
compact flash signals based on CFNWE.
representation of this logic. No external logic is required if I/O mode is not used (in this case,
CNFWE signal can drive directly _WE compact flash signal).
Attribute memory mode, common memory mode and I/O mode are supported by writing the
address setup and hold time on the NCS[4] (and/or NCS[5]) chip select to the appropriate val-
ues. For details on these signal waveforms, please refer to the section: Setup and Hold Cycles
of the SMC Section.
Common Memory
Attribute Memory
I/O Mode
Mode
CFCE1 and CFCE2 Truth Table
CFCE2
NBS1
NBS1
NBS1
1
1
Figure 14-3 on page 170
CFCE1
NBS0
NBS0
NBS0
0
0
Table 14-5 on page 169
16 bits
16 bits
16bits
DBW
8 bits
8 bits
Figure 14-3 on page 170
Comment
Access to Even Byte on
DATA[7:0]
Access to Even Byte on
DATA[7:0]
Access to Odd Byte on
DATA[15:8]
Access to Odd Byte on
DATA[7:0]
Access to Even Byte on
DATA[7:0]
Access to Odd Byte on
DATA[15:8]
Access to Odd Byte on
DATA[7:0]
demonstrates a schematic representation of
to enable the required access type.
demonstrates a schematic
SMC Access
Mode
Byte Select
Byte Select
Byte Select
169