AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 820

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.6.2.1
32072G–11/2011
Command - Response Operation
The structure of commands, responses and data blocks is described in the MultiMedia-Card
System Specification. Refer also to
MultiMediaCard bus data transfers are composed of these tokens.
There are different types of operations. Addressed operations always contain a command and a
response token. In addition, some operations have a data token; the others transfer their infor-
mation directly within the command or response structure. In this case, no data token is present
in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the MCI
clock (CLK).
Two types of data transfer commands are defined:
Both read and write operations allow either single or multiple block transmission. A multiple
block transmission is terminated when a stop command follows on the CMD line similarly to the
sequential read or when a multiple block transmission has a pre-defined block count
tion “30.6.3” on page
The MCI provides a set of registers to perform the entire range of MultiMedia Card operations.
After reset, the MCI is disabled and becomes valid after setting the Multi-Media Interface Enable
bit in the Control Register (CR.MCIEN).
The Power Save Mode Enable bit in the CR register (CR.PWEN) saves power by dividing the
MCI clock (CLK) by 2
in the Mode Register (MR.PWSDIV).
The two bits, Read Proof Enable and Write Proof Enable in the MR register (MR.RDPROOF and
MR.WRPROOF) allow stopping the MCI Clock (CLK) during read or write access if the internal
FIFO is full. This will guarantee data integrity, not bandwidth.
All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification.
The two bus modes (open drain and push/pull) needed to process all the operations are defined
in the Command Register (CMDR). The CMDR register allows a command to be carried out.
For example, to perform an ALL_SEND_CID command
Table 30-4.
CMD
• Sequential commands: these commands initiate a continuous data stream. They are
• Block-oriented commands: these commands send a data block succeeded by CRC bits.
terminated only when a stop command follows on the CMD line. This mode reduces the
command overhead to an absolute minimum.
S
T
ALL_SEND_CID command
Host Command
Content
PWSDIV
822.).
CRC
+ 1 when the bus is inactive. The Power Saving Divider field locates
E
Table 30-5 on page
Z
N
ID
******
Cycles
Z
S
821.
T
Content
CID
Z
Z
Z
(See Sec-
820