AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 67

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.6.10
Name:
Access Type:
Offset:
Reset Value:
• BOD33DET: Brown out detection
• BODDET: Brown out detection
• OSC32RDY: 32 KHz oscillator Ready
• OSC1RDY: Oscillator 1 Ready
• OSC0RDY: Oscillator 0 Ready
• MSKRDY: Mask Ready
• CKRDY: Clock Ready
32072G–11/2011
OSC0RDY
31
23
15
7
-
-
-
This bit is set when a 0 to 1 transition on POSCSR.BOD33DET bit is detected:
going below BOD33 reference value.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set when a 0 to 1 transition on POSCSR.BODDET bit is detected:
below BOD reference value.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set when a 0 to 1 transition on the POSCSR.OSC32RDY bit is detected:
ready to be used as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set when a 0 to 1 transition on the POSCSR.OSC1RDY bit is detected:
used as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set when a 0 to 1 transition on the POSCSR.OSC1RDY bit is detected:
used as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
This bit is set when a 0 to 1 transition on the POSCSR.MSKRDY bit is detected:
(CPU/HSB/PBA/PBB)_MASK registers.
This bit is cleared when the corresponding bit in ICR is written to one.
0: The CKSEL register has been written, and the new clock setting is not yet effective.
1: The synchronous clocks have frequencies as indicated in the CKSEL register.
Note: Writing a one to ICR.CKRDY has no effect.
Interrupt Status Register
MSKRDY
30
22
14
6
-
-
-
ISR
Read-only
0x4C
0x00000000
CKRDY
29
21
13
5
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
-
BOD has detected that power supply is going
BOD33 has detected that power supply is
Clocks are now masked according to the
26
18
10
Oscillator 1 is stable and ready to be
Oscillator 1 is stable and ready to be
2
-
-
-
-
The 32 KHz oscillator is stable and
OSC32RDY
BOD33DET
LOCK1
25
17
9
1
-
OSC1RDY
BODDET
LOCK0
24
16
8
0
-
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