NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 97

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.8.5
3.8.5.1
3.8.5.2
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Boot and Reset Registers
SYRE - System Reset Register
This register controls MCH reset behavior. Any resets produced by a write to this
register must be delayed until the configuration write is completed on the initiating
interface (PCI Express, ESI, processor bus, SMBus, JTAG).
There is no “SOFT RESET” bit in this register. That function is invoked through the ESI.
There are no CORE:FBD gear ratio definitions in this register. Those are located in the
DDRFRQ register.
CPURSTCAPTMR: CPU Reset Done Cap Latency Timer
This
CPU_RST_DONE_ACK using a 12-bit variable timer.
Device:
Function:
Offset:
Version:
12:11
7:0
Bit
15
14
13
10
9
8
register
RWST
ROST
Attr
RW
RW
RW
RV
RV
RV
16
0
40h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
implements
Default
0h
0
0
0
0
0
0
0
SAVCFG: Preserve Configuration
When this bit is set, MCH configuration register contents (except for this bit)
are not cleared by hard reset. As this bit is cleared by reset, software must
set it after each reset if this behavior is desired for the next reset. If this bit
is set, BOFL will not be cleared by reset. Software should use the Boot Flag
Reset bit to re-enable the BOFL mechanism.
CPURST: Processor Reset
If set, the MCH will assert processor RESET# on both buses as soon as the
MCH has no pending transactions. The chipset will then deassert RESET#
following the timing rules described in the Reset Chapter.
The MCH does not have any mechanism to drain transactions before effecting
the CPU RESET#. It is the responsibility of software to ensure that the
system is quiet before sending the configuration write (last command) to set
this field in the MCH in order to drive the CPU RESET# signal. Any violation of
this usage pattern would render the system unstable and potentially
catastrophic.
CPUBIST: Processor Built-In-Self-Test
If set, A[3]# is asserted during Power-On-Configuration (POC), and the
processor will run BIST before engaging processor bus protocol.
Reserved1
S3: S3 Sleep State
The MCH sets this bit when it sends an Ack-S3 message to the ESI port.
The MCH clears this bit after it has placed appropriate FB-DIMM channels into
the FB-DIMM.Calibrate state in response to deassertion of the RESETI#
signal.
ROR: Processor Reset on Refresh
If set, the MCH will assert processor RESET# on both busses when a refresh
cycle completes.
BNR_INDP_BINIT_MODE: BNR independent of BINIT Mode
0: The Chipset associates BNR with BINIT and for CPUs that do NOT follow
the “BNR independent of BINIT” feature set.
1: Enables the Chipset to use the “BNR independent of BINIT” feature set. i.e
no dependency is required between BNR and BINIT.
Refer to the BNR#, BINIT# sampling rules in the Intel® Pentium® 4 and
Intel® Xeon® Processor External Hardware Specification, Rev 2.5,
Ref#14035
Reserved
the
cap
latency
method
Description
for
the
CPU_RST_DONE/
97