NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 138

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.8.11
3.8.11.1
3.8.11.2
138
PCI Express Capability Structure
The PCI Express capability structure describes PCI Express related functionality,
identification and other information such as control/status associated with the port. It
is located in the PCI 2.3 compatible space and supports legacy operating system by
enabling PCI software transparent features.
PEXCAPL[7:2, 0]- PCI Express Capability List Register
The PCI Express Capability List register enumerates the PCI Express Capability
structure in the PCI 2.3 configuration space.
PEXCAP[7:2, 0] - PCI Express Capabilities Register
The PCI Express Capabilities register identifies the PCI Express device type and
associated capabilities.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:14
15:8
7:0
Bit
Bit
Attr
Attr
RO
RO
RV
0, 2-3
0
6Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
6Ch
Intel 5000Z Chipset
4-7
0
6Ch
Intel 5000P Chipset
0, 2-3
0
6Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
6Eh
Intel 5000Z Chipset
4-7
0
6Eh
Intel 5000P Chipset
Default
Default
00h
10h
0h
NXTPTR: Next Ptr
This field is set to NULL pointer to terminate the PCI capability list.
CAPID: Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.
Reserved.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description