NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 45

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3
3.1
i
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Register Description
The MCH contains three sets of software accessible registers, accessed via the host
processor I/O address space:
The MCH supports PCI configuration space accesses using the mechanism denoted as
Configuration Mechanism 1 in the PCI specification as defined in the PCI Local Bus
Specification, Revision 2.3. All the registers are organized by bus, device, function, and
so forth, as defined in the PCI-Express Base Specification, Revision 1.0a. The MCH
supports registers in PCI Express extended space. All MCH registers in Intel 5000P
Chipset appear on PCI Bus #0.
In addition, the MCH registers can be accessed by a memory mapped register access
mechanism (as MMIO), a PCI configuration access mechanism (only PCI space
registers), and register access mechanisms through JTAG and SMBus. The memory
mapped access mechanism is further broken down into different ranges. The internal
registers of this chip set can be accessed in 8-bit, 16-bit, or 32-bit quantities, with the
exception of CFGADR which can only be accessed as a 32-bit. All multi-byte numeric
fields use “little-endian” ordering (that is, lower addresses contain the least significant
parts of the field).
In addition, the MCH can forward accesses to all PCI/PCI Express configuration
registers south of the MCH through the same mechanisms.
Register Terminology
Registers and register bits are assigned one or more of the following attributes. These
attributes define the behavior of register and the bit(s) that are contained with in. All
bits are set to default values by hard reset. Sticky bits retain their states between hard
resets.
RO
WO
RW
RC
RCW
RWC
• Control registers I/O mapped into the processor I/O space that controls access to
• Internal configuration registers residing within the MCH are partitioned into logical
PCI configuration spaces.
device register sets (“logical” since they reside within a single physical device). The
first register set is dedicated to MCH functionality (controls PCI bus 0, that is,
DRAM configuration, other chipset operating parameters, and optional features).
The second register set is dedicated to ESI control. The third register set is
dedicated to ESI control.
Term
Read Only. If a register bit is read only, the hardware sets its state. The bit may be read
by software. Writes to this bit have no effect.
Write Only. The register bit is not implemented as a bit. The write causes some
hardware event to take place.
Read/Write. A register bit with this attribute can be read and written by software.
Read Clear: The bit or bits can be read by software, but the act of reading causes the
value to be cleared.
Read Clear/Write: A register bit with this attribute, will get cleared after the read. The
register bit can be written.
Read/Write Clear. A register bit with this attribute, can be read or cleared by software.
In order to clear this bit, a one must be written to it. Writing a zero will have no effect.
Description
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