NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 284

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.3.6
4.3.7
Figure 4-3.
284
Chipset Specific Range
The address range FE00 0000h - FEBF FFFFh region is reserved for chipset specific
functions.
FE00 0000h - FE00 8000h: This range (with size of 128 KB for four FB-DIMM
channels; 16 Advanced Memory Buffer (AMB) per channel, 2 KB per AMB), is used for
accessing AMB registers. These registers can only be accessed through memory
mapped register access mechanism as MMIO. Notice that they are not accessible
through CF8/CFC or MMCFG which are used for PCI/PCI Express configuration space
registers. This range could be relocated by programming AMBASE register. The
AMBASE register could also be accessed through a fixed location.
FE60 0000h - FE6F FFFFh: This range is used for fixed memory mapped Intel 5000P
Chipset registers. They are accessible only from the processor bus. These registers are
fixed since they are needed early during the boot process. The registers include:
These registers are described in the Intel 5000P Chipset MCH Configuration Register,
Chapter 3, “Register Description.”
requests to the remainder of this region unless they map into one of the relocatable
regions such as MMCFG. The mechanism for this range can be the same as it is for the
memory mapped configuration accesses.
Interrupt/SMM Region
This 4 MB range is used for processor specific applications. This region lies between
FEC0 0000h and FEFF FFFFh and is split into four 1 MB segments.
Interrupt /SMM Region
• Four Scratch Pad Registers
• Four Sticky Scratch Pad Registers
• Four Boot flag registers
• HECBASE register for MMCFG
• AMBASE register for AMB memory mapped registers
F E 0 0 0 0 0 0 h
F E E 0 0 0 0 0 h
F E D 3 F F F F h
F E D 2 0 0 0 0 h
F E C 9 0 0 0 0 h
F E C 8 F F F F h
F D E A
F E F F F F F F h
F E E F F F F F h
F D E B F F F F h
0 0 0 0 h
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
The Intel 5000P Chipset MCH will master abort
6 3 2 x E S B I / O C o n tro lle r H u b
6 3 2 x E S B I / O C o n tro lle r H u b
( M M T = F E D 0 0 0 0 h - F E D 0
3 F F F h )
R o u te to
R o u te to In te l®
6 3 2 x E S B I / O C o n tro lle r H u b
6 3 2 x E S B I / O C o n tro lle r H u b
R o u te to
R o u te to
In te l® 6 3 1 x E S B /
H ig h S M M
I / O A P IC
R e s e rv e d
In te rru p t
In te l® 6 3 1 x E S B /
In te l® 6 3 1 x E S B /
6 3 1 x E S B /
System Address Map