NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 103

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
Table 3-32. When Will a Intel 5000P Chipset PCI Express Device be Accessible?
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
(Sheet 2 of 2)
Figure 3-4
software. Each PCI Express port’s configuration space has four regions:
Express
• Standard PCI Header - This region closely resembles a standard PCI-to-PCI
• PCI Device Dependent Region - The region is also part of standard PCI
• PCI Express Extended Configuration Space - This space is an enhancement
• Capability Working Register Sets - These ranges are indirectly accessed
Port
PCI
bridge header.
configuration space and contains the PCI capability structures. For the Intel 5000P
Chipset MCH, the supported capabilities are:
beyond standard PCI and only accessible with PCI Express aware software. The
MCH supports the Enhanced Error Signalling capability.
through Data and Select registers in the capability structures. For the MCH,
working register sets exist for the Standard hot-plug Controller and Power
Management capabilities.
3
2
0
— Message Signalled Interrupts
— Hot-plug
— PCI Express Capability
illustrates how each PCI Express port’s configuration space appears to
Device
3
2
0
possible
combination
ESI - Not
combinable
x8
Port3 is connected to a 4x device
Port2 is connected to a x4 or x8 device
Port0 is connected to a x4 Intel 631xESB/632xESB I/O
Controller Hub port through ESI and cannot be combined with
any other port
Registers may be accessed if:
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