NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 256

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.10.5
3.10.6
3.10.7
3.10.8
256
CAPPTR: Capability Pointer Register
INTL: Interrupt Line Register
The Interrupt Line register is used to communicate interrupt line routing informaiton
between initialization code and the device driver. The Intel 5000 Series MCH does not
have a dedicated interrupt line and is not used.
INTP: Interrupt Pin Register
The INTP register identifies legacy interrupts for INTA, INTB, INTC and INTD as
determined by BIOS/firmware. These are emulated over the ESI port using the
Assert_Intx commands as appropriate.
Power Management Capability Structure
The DMA engine integrated device within the MCH incorporates power management
capability with D0 (working) and a pseudo D3 hot/cold states (sleep) that can be
controlled independently through software. From a software perspective, the D3 states
convey information to the power controller that the device is in the sleep mode though
the physical entity inside the chipset may be fully powered. During transition
to D3, it will ensure that all pending DMA Channels are completed in full.
Device:
Function:
Offset:
Version:
7:0
Device:
Function:
Offset:
Version:
7:0
Device:
Function:
Offset:
Version:
Bit
Bit
7:0
Bit
RO
RWO
Attr
Attr
RWO
Attr
8
0
34h
Intel 5000P Chipset
8
0
3Ch
Intel 5000P Chipset
8
0
3Dh
Intel 5000P Chipset
50h
00h
Default
Default
Default
01h
CAPPTR: Capability Pointer
This register field points to the first capability. PM structure in the DMA Engine
device.
INTL: Interrupt Line
BIOS writes the interupt routing information to this register to indicate which input
of the interrupt controller this PCI-Exress Port is connected to. Not used in the Intel
5000 Series MCH since the PCI-Express port does not have an interrupt lines.
INTP: Interrupt Pin
This field defines the type of interrupt to generate for the PCI Express port.
001: Generate INTA
010: Generate INTB
011: Generate INTC
100: Generate INTD
Others: Reserved
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Description
Register Description
1
from D0