NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 340

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

5.11
Figure 5-15. MCH to Intel 631xESB/632xESB I/O Controller Hub Enterprise South Bridge
340
Any error in the data part of an interrupt message, interrupt acknowledge, or EOI will
be treated the same way as data error with any other transaction – single bit errors will
be corrected by ECC, double bit error will be treated and logged as uncorrectable. For
more details on error handling, please refer to the RAS chapter.
Enterprise South Bridge Interface (ESI)
The Enterprise South Bridge Interface (ESI) in the Intel 5000P Chipset north bridge is
the chip-to-chip connection to the Intel 631xESB/632xESB I/O Controller Hub see
Figure
special commands/features added to enhance the PCI Express interface for enterprise
applications. This high-speed interface integrates advanced priority-based servicing
allowing for concurrent traffic. Base functionality is completely transparent permitting
current and legacy software to operate normally. For the purposes of this document,
the Intel 631xESB/632xESB I/O Controller Hub will be used as a reference point for
the ESI discussion in the Intel 5000P Chipset north bridge.
Interface
The ESI port in the Intel 5000P Chipset north bridge may be combined with two
additional PCI Express ports to augment the available bandwidth to the Intel 631xESB/
632xESB I/O Controller Hub. When operating alone the available bi-directional
bandwidth to the Intel 631xESB/632xESB I/O Controller Hub is 2 GB/s (1 GB/s each
direction). When the ESI is pared with 2 additional x4 PCI Express links the available
bi-directional bandwidth to the Intel 631xESB/632xESB I/O Controller Hub is increased
to 6 GB/s. The details of how the ESI port is combined with additional x4 PCI Express
ports are covered in
5-15. The ESI is an extension of the standard PCI Express specification with
Section
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
5.13.3.
In te l® 6 3 1 x E S B / 6 3 2 x E S B I/ O
C o n tro lle r H u b
P o rt 0
T ra n s a c tio n
T ra n s a c tio n
D M I
P h y s ic a l
P h y s ic a l
M C H
L in k
L in k
Functional Description