NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 50

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Figure 3-2.
3.4
.
Table 3-1.
50
PCI Express Config
Txns (including
ESI)
PCI Express
MMCFG
on FSB
PCI Express
MMCFG
from ESI or PCI
Express
CONFIG_ADDRESS
If the cycle is forwarded to the Intel 631xESB/632xESB I/O Controller Hub via ESI, the
Intel 631xESB/632xESB I/O Controller Hub compares the non-zero Bus Number with
the Secondary Bus Number and Subordinate Bus Number Registers of its PCI-to-PCI
bridges to determine if the configuration cycle is meant for primary PCI bus, one of the
Intel 631xESB/632xESB I/O Controller Hub’s PCI Express ports, or a downstream PCI
bus.
Type 1 Configuration Address to PCI Address Mapping
Device Mapping
Each component in a Intel 5000P Chipset-based system is uniquely identified by a PCI
bus address consisting of; Bus Number, Device Number and Function Number. Device
configuration is based on the PCI Type 0 configuration conventions. All PCI devices
within a Intel 5000P Chipset-based platform must support Type 0 configuration
accesses. All MCH registers in the Intel 5000P Chipset MCH appear on Bus #0.
All Intel 5000P Chipset MCH configuration registers reside in the configuration space
defined by Bus, Device, Function, Register address. Some registers do not appear in all
portions of this space and some mechanisms do not access all portions of this space. In
general the configuration space is sparsely populated. The following table defines
where the various fields of configuration register addresses appear. Each row defines a
different access mechanism, register, interface, or decoder. Each column defines a
different field of the configuration address.
Configuration Address Bit Mapping
PCI Address
Destination
Source
Not permitted to access MCH or FB-DIMM regs and will be master aborted.
Destination
Source/
AD[31:0]
31
Bus[7:0]
A[27:20]
3
1
1
3
0
Bus
Reserved
0
2
4
2
4
Device[4:0]
A[19:15]
2
3
2
3
Device
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Bus Number
Number
Bus
16 15
16 15
Function[2:0
]
A[14:12]
Device Number
Function
Number
Device
11
1
1
Extended
Register
Addr[3:0]
A[11:8]
1
0
Function Number
Function Number
1
0
[11:8]
Dword
Offset
8
8 7
Register
[5:0]
BE[7:4]
A[7:3]
7
Reg. Index
[5:0]
Index
Reg.
2 1
2
Register Description
1st DW
BE[3:0]
BE[7:0]
1
Byte in
X X
Dword
0 1
0
0
Fmt,
Type
n/a
Type