NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 272

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.11.7
3.11.8
272
PEX[7:2,0]IBDLYSYM: PEX IBIST Delay Symbol
This register stores the value of the delay symbol used in lane inversion cross-talk
testing. Only valid PCI Express control characters/symbols are allowed for IBIST
testing.
PEX[7:2,0]IBLOOPCNT: PEX IBIST Loop Counter
This register stores the current value of the loop counter.
Device:
Function: 0
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function: 0
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
15:12
15:9
11:0
8:0
Bit
Bit
Attr
Attr
RW
RO
RV
RV
3-2, 0
38Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
7-4
38Ch
Intel 5000P Chipset
4-5
0
38Ch
Intel 5000Z Chipset
3-2, 0
0
38Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
38Eh
Intel 5000Z Chipset
7-4
0
38Eh
Intel 5000P Chipset
Default
Default
1BCh
000h
0h
0h
Reserved
DLYSYM: Delay Symbol
This is the 9-bit delay symbol value used (default is K28.5).
Reserved
LOOPCNTVAL: Loop Count Value
Once the IBIST is engaged, loop counts are incremented when a set of 8 symbols
has been received. If an error occurs, this register reflects the loop count value of
the errant Rx lane. If there is no error then this register reads 00h.
Note: Since each receiver is not deskewed with respect to the IBIST pattern
generator we cannot have a coherent loop count value with N number of receivers
and only one loop counter. It would require additional logic to select which
receiver indicates the count.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
Description
Description
Register Description