NQ5000P S L9TN Intel, NQ5000P S L9TN Datasheet - Page 53

• Manufacturer Part Number: NQ5000P S L9TN
• Manufacturer: Intel

Specifications of NQ5000P S L9TN

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Register Description
3.5
3.5.1
Table 3-5.
3.5.2
Table 3-6.
Intel® 5000P/5000V/5000Z Chipset Memory Controller Hub (MCH) Datasheet
I/O Mapped Registers
There are only two I/O addresses that affect Intel 5000P Chipset MCH state. The first
address is the DWORD location (CF8h) references a read/write register that is named
CONFIG_ADDRESS. The second DWORD address (CFCh) references a read/write
register named CONFIG_DATA. These two addresses are used for the PCI CFCh / CF8h
configuration access mechanism.
CFGADR: Configuration Address Register
CFGADR is written only when a processor I/O transaction to I/O location CF8h is
referenced as a DWord; a Byte or Word reference will not access this register, but will
generate an I/O space access. Therefor the only I/O space taken up by this register is
the DWORD at location CF8h. I/O devices that share the same address but use BYTE or
WORD registers are not affected because their transactions will pass through the host
bridge unchanged.
The CFGADR register contains the Bus Number, Device Number, Function Number, and
Register Offset for which a subsequent CFGDAT access is intended. The mapping
between fields in this register and PCI Express configuration transactions is defined by
Table
I/O Address: CF8h
CFGDAT: Configuration Data Register
CFGDAT provides data for the 4 bytes of configuration space defined by CFGADR. This
register is only accessed if there is an access to I/O address, CFCh on the processor bus
and CFGADR.CFGE (configuration enable) bit is set. The byte enables with the I/O
access define how many configuration bytes are accessed.
I/O Address: CFCh
30:24
23:16
15:11
10:8
31:0
7:2
1:0
Bit
Bit
31
3-1.
Attr
Attr
RW
RW
RW
RW
RW
RW
RW
RV
Default
Default
00h
00h
00h
0h
0h
0h
0h
0
Configuration Data Window
The data written or read to the configuration register (if any) specified by
CFGADR
CFGE: Configuration Enable
Unless this bit is set, accesses to the CFGDAT register will not produce a
configuration access, but will be treated as other I/O accesses. This bit is
strictly an enable for the CFC/CF8 access mechanism and is not forwarded to
ESI or PCI Express.
Reserved.
Bus Number
If 0, the MCH examines device to determine where to route. If non-zero, route
as per PBUSN and SBUSN registers.
Device Number
This field is used to select one of the 32 possible devices per bus.
Function Number
This field is used to select the function of a locally addressed register.
Register Offset
If this register specifies an access to MCH registers, this field specifies a group
of four bytes to be addressed. The bytes accessed are defined by the Byte
enables of the CFGDAT register access
Writes to these bits have no effect, reads return 0
Description
Description
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